(a) Field of the Invention
The present invention relates to a method for designing a system LSI (large-scale integrated circuit) and, more particularly, to a method for designing a system LSI by employing a software-hardware-collaborated (SHC) design system using a behavior synthesis. The present invention also relates to a recording medium for storing therein the software defining the method for designing such a system LSI.
(b) Description of the Related Art
In recent years, a system LSI, or system-on-chip LSI, is increasingly used which realizes all the circuit functions of a desired system on a single chip. In addition, along with the finer fabrication process of the semiconductor devices, the number of logic gates integrated on a system LSI has increased dramatically, wherein the system LSI has a higher processing performance accordingly.
The system LSIs are used for a variety of processings such as image processing, encryption, filtering, and decoding, wherein the input/output signals have a variety of formats, and a variety of algorithms are used for processing these signals. In addition, the system LSIs have a variety of throughputs depending on the performances requested for the processing. In the recent trend, the algorithms used in the system LSI become more and more complicated, and the throughputs for the processing are significantly improved.
For the reasons as described heretofore, the recent system LSIs are designed for dedicated processing for the signals used therein.
FIG. 6 shows a flowchart for designing a system LSI by using a conventional SHC design system. In general, in the SHC design system using a behavior synthesis, an algorithmic description D1 described in a general-purpose language such as C language, or another higher-level language such as a dedicated language used for the behavior level description is translated into a lower-level-language description, such as a logic synthesis RTL (register transfer level) description D9. The RTL description can be implemented as hardware by using hardware resources including memory devices such as a register, and processors such as an adder.
The algorithmic description D1 describes all the functions of the system LSI in a behavior level. If the most part of the functions of the algorithm description D1 are to be implemented by hardware, the system LSI has a larger circuit scale and is thus expensive, although the system LSI has a higher throughput for the processing. On the other hand, if the most part of the functions are to be implemented by software, the system LSI has a lower throughput, although the system LSI has a smaller circuit scale.
Accordingly, in the initial stage of the design, as shown in FIG. 6, the functions described in the algorithmic description D1 are separated into two groups in consideration of the constraints (or settings) for the system LSI, including circuit scale, throughput performance for processing, cost etc. (step S201). The two groups include a first group implemented by hardware resources, and a second group implemented by software resources.
If all the hardware resources are designed for all the details thereof, the development for the hardware resources will take higher cost and longer time length. For this reason, hardware macros designed in the past and stored as hardware intellectual property (IP) are reused for the design, by utilizing the stored resources as much as possible. The hardware IP is generally designed in consideration of reuse feasibility and higher versatility, and thus is installed with ease in the architecture of the system LSI.
The hardware of processor is designed as a combination of a basic-instruction processor 15 such as a microprocessor for processing versatile calculations and a dedicated-instruction processor 16 dedicated to specific processings such as a signal input/output processing. A hardware IP designed before and stored in the database is generally used as the basic-instruction processor 15. The basic-instruction processor 15 is generally designed by another division in the semiconductor manufacturer other than the division which develops the system LSI, the another division being dedicated to designing processors by using a register transfer design technique. The description for the basic-instruction processor 15 is presented together with a simulation description D10a. 
After the basic-instruction processor 15 to be used in the system LSI is determined, the design process advances to a design for the dedicated-instruction processor 16 (step S202). In the design for the dedicated-instruction processor 16, the functions thereof are described in a higher-level language. By behavior synthesis of descriptions for the dedicated-instruction processor, a RTL description D9b and a simulation description D10b of the dedicated-instruction processor are obtained (step S203). It is judged in step S204 whether or not the RTL description D9b of the dedicated-instruction processor 16 can realize a circuit scale within a setting previously established as a constraint for the system LSI.
If the circuit scale is above the setting, the process returns to step S201, wherein the design for the system LSI is iterated from the first. If it is judged in step S204 that the circuit scale is within the setting, the RTL description D9a of the basic-instruction processor 15 and the description D9b of the dedicated-instruction processor 16 are coupled together via the RTL description 9c of the buses (step S205).
Subsequently, in the software design, application programs 11 and a device driver 14 for operating the dedicated-instruction processor 16 from the basic-instruction processor 15 are defined in a high-level language (step S206). The application programs 11 and the device driver 14 are compiled in a compiler (compiler/assembler/linker) and translated into a machine-language instruction set 13 (step S207). The machine-language instruction set 13 thus obtained, the simulation descriptions D10a and D10b and the bus simulation description D10c are combined together to form an overall simulation description, which is input to an instruction set simulator (step S208), wherein a simulation is performed in an environment similar to the architecture of the system LSI.
By simulating the hardware and software in the instruction set simulator, it is examined or verified that there is no error in the design of the hardware and software (step S209). In step S209, the throughput performance in the time domain and the power consumption of the system LSI are also measured under the actual service condition, and it is judged whether or not the throughput thus measured satisfies the performance required of the system LSI (step S210). If the result of judgement is negative, the process returns to step S201, wherein the separation of functions into software and hardware groups is corrected. If the result of judgement is affirmative in step S210, the design for the system LSI is fixed, followed by performing logic synthesis of the RTL description D9a of the basic-instruction processor 15, the RTL description D9b of dedicated-instruction processor 16, and the bus RTL description D9c to determine the actual gate circuit of the system LSI.
The conventional design for a system LSI, as described above, uses the technique for adding the dedicated-instruction processor 16 executing new dedicated instructions to the basic-instruction processor 15 executing general instructions. The execution of the basic instructions and dedicated instructions in a single processor necessitates a design of a new processor each time a system LSI is to be designed. This raises a problem in that the development of such a new processor takes considerable cost and time length.
An “Xtensa” processor was recently proposed which can restructure a basic processor architecture in a user-specific LSI by changing the resources thereof, such as the memory size, based on the settings (or constraints) such as number of gates, throughput performance and power dissipation (refer to Design Wave Magazine 1999, December). The proposed processor allows a DSP unit or a dedicated instruction unit, such as a numerical calculation coprocessor, to be selected and added, and also allows use of an extended language such as a TIE language for definition of new dedicated instruction algorithms. However, in this processor, since the dedicated instructions are defined separately from the basic-instruction processor to be restructured, a new dedicated instruction cannot be added by defining the same with reference to a basic instruction now existing in the basic processor.
Another processor called VUPU processor is also known which has dedicated instructions obtained by behavior synthesis which translates the language of the behavior level description of the dedicated-instruction processor architecture into the RTL description. The VUPU processor can be operated by the instruction delivered from the basic-instruction processor (refer to Design Wave Magazine1999, December).
The proposed VUPU processor includes a PU section (basic section) for executing a P-instruction defined in the basic instructions and a VU section (dedicated section) for executing a V-instruction defined by combining a plurality of P-instructions. This reduces the time length for the design of processor compared to the case of design for a new processor, because it is sufficient in this technique only to add V-instructions in the processor for the design of a system LSI.
However, in the VUPU processor as described above, an interface is defined for communication between the PU section and the VU section, and in addition, the basic-instruction processor architecture and the dedicated-instruction processor architecture are separated from each other. Accordingly, if a V-instruction which includes therein a function similar to a P-instruction is desired for definition, it is not possible to use, in the desired V-instruction, a part of the functional block of the P-instruction although it is optimized for a hardware macro block. In addition, since the P-instructions are defined in a fixed architecture of the P-instruction set, some P-instructions which are not needed in a specific system LSI may be included therein depending the type of the specific system LSI.